The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device provided with an on-chip or built-in test circuit.
The capacity of semiconductor memories has been increasing remarkably, and memory having 256 kbit are currently manufactured. Also, many prototype one megabit dynamic memories have been announced. However, accompanied by the increase in memory capacity, the test time for testing memories also has been increased.
In order to determine whether a memory is good or not, it is necessary to check all the memory cells. The test of a memory is conducted by writing a predetermined one of binary logic data into each memory cell and reading stored data from each memory cell. If the predetermined one of binary logic data is read from one memory cell, this one memory cell is judged as a good cell. If a logic data other than the above predetermined logic data is read from one memory cell, then this one memory cell is judged as a default cell. This testing is conducted for all the memory cells.
The above kind of test must be performed under varying conditions of power supply voltge, timing of signals or the like. Thus, the test time has been increased largely in proportion to the capacity of memories. For example, a typical test time required for a 64-Kbit memory is 3.2 second, while the test times for a 256-Kbit memory and a 1-Mbit memory are 12.8 seconds and 51.2 seconds, respectively. The increase in test time also has increased the cost of manufacturing memories.